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specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 10511 sy/40809 sy /20080822-s000015 no.na1310-1/14 LE25LA322 overview the LE25LA322 is a 32kbit eeprom that su pports serial peripheral interface (spi). it realizes high speed operation and high level reliability by incorpora ting sanyo?s high performance cmos eeprom technology. the interface is compatible with spi bus protocol, therefore, it is best suited for applications that require small-scale rewritable nonvolatile parameter memory. moreover, the LE25LA322 has a 32 bytes page rewrite function that provides rapid data rewriting. features ? capacity : 32kbits (4k8bits) ? single supply voltage : 1.8v to 3.6v ? serial interface : spi mode0, mode3 supported ? operating clock frequency : 5mhz (2.5v to 3.6v), 3mhz (1.8v to 3.6v) ? low current dissipation : standby : 3 a (max.) : active (read) : 1ma (max.) : active (rewrite) : 3ma (max.) ? page write function : 32bytes ? rewrite time : 10ms ? number of rewrite times : 10 5 times/address,10 6 times/page(page=32byte) ? data retention period : 20years ? high reliability : adopts sanyo?s proprietary symme tric memory array configuration (usp6947325) incorporates a feature to prohibit write operations under low voltage conditions. orderin g number : ena1310b serial spi eeprom (spi bus) (32kbit) * this product is licensed from silicon storage technology, inc. (usa), and manufactured and sold by sanyo semiconductor co., l td.
LE25LA322 no.na1310-2/14 package dimensions unit : mm (typ) unit : mm (typ) 3032e [LE25LA322m] 3245b [LE25LA322tt] packages mfp8 (225mil) : LE25LA322m msop8 (150mil) : LE25LA322tt pin assignment pin descriptions pin.1 cs chip select pin.2 so serial data output pin.3 wp write protect pin.4 v ss ground pin.5 si serial data input pin.6 sck serial clock pin.7 hold hold pin.8 v dd power supply block diagram address buffers & latches x- decoder eeprom cell array y-decoder i/o buffers & data latches control logic serial interface cs sck si so wp hold sanyo : msop8(150mil) 3.0 1.1max 3.0 0.5 4.9 12 8 0.25 0.65 (0.53) (0.85) 0.125 0.08 cs so wp v ss v dd hold sck si 1 2 3 4 8 7 6 5 sanyo : mfp8(225mil) 12 8 5.0 0.63 6.4 0.15 0.35 1.27 (0.6) 4.4 (1.5) 1.7 max 0.1
LE25LA322 no.na1310-3/14 specifications absolute maximum rating /if an electrical stress exceeding the maximum ra ting is applied, the device may be damaged. parameter symbol conditions ratings unit storage temperature -65 to +150 c supply voltage -0.5 to 4.6 v dc input voltage -0.5 to v dd +0.5 v overshoot voltage (below 20ns) -1.0 to v dd +0.5 v operating conditions parameter symbol conditions ratings unit operating temperature -40 to +85 c operating supply voltage 1.8 to 3.6 v dc electrical characteristics parameter symbol conditions min typ max unit cs = 0.1v dd , hold = wp = 0.9v dd si = 0.1v dd /0.9v dd , so = open operating frequency = 5mhz, v dd = 3.6v 1ma cs = 0.1v dd , hold = wp = 0.9v dd si = 0.1v dd /0.9v dd , so = open operating frequency = 5mhz, v dd = 2.5v 0.5 ma supply current when reading i ccr cs = 0.1v dd , hold = wp = 0.9v dd si = 0.1v dd /0.9v dd , so = open operating frequency = 3mhz, v dd = 1.8v 0.3 ma supply current when writing i ccw v dd = 3.6v., v in = 0.1v dd /0.9v dd 3ma cs = v dd , v in = v dd or v ss v dd = 3.6v 3 a cmos standby current i sb cs = v dd , v in = v dd or v ss v dd = 2.5v 2 a input leakage current i li v in = v ss to v dd , v dd = v dd max. -2 2 a output leakage current i lo v in = v ss to v dd , v dd = v dd max. -2 2 a input low voltage v il v dd = v dd max. -0.3 0.3v dd v input high voltage v ih v dd = v dd min. 0.7v dd v dd +0.3 v v ol1 i ol = 2.0ma, v dd = 3.6v 0.4 v v ol2 i ol = 1.5ma, v dd = 2.5v 0.4 v output low voltage v ol3 i ol = 0.15ma, v dd = 1.8v 0.3 v v oh1 i oh = -2.0ma, v dd = 3.6v 0.8v dd v v oh2 i oh = -0.4ma, v dd = 2.5v 0.8v dd v output high voltage v oh3 i oh = -0.1ma, v dd = 1.8v 0.8v dd v capacitance at ta = 25 c, f = 1.0mhz parameter symbol conditions min typ max unit output pin capacitance c dq v dq = 0v 12 pf input pin capacitance c in v in = 0v 6pf note : these parameters are sampled and not 100% tested. ac electrical characteristics input pulse level 0.2v dd to 0.8v dd input pulse rise/fall time 10ns output detection voltage 0.5v dd output load 30pf
LE25LA322 no.na1310-4/14 ac characteristics (at fclk = 5mhz)/v dd = 2.5v to 3.6v parameter symbol conditions min typ max unit clock frequency fclk 5 mhz sck logic high level pulse width t clhi 90 ns sck logic low level pulse width t cllo 90 ns input signal rise/fall time t rf 1us cs setup time t css 90 ns sck setup time t cls 90 ns data setup time t ds 20 ns data hold time t dh 30 ns cs hold time t csh 90 ns sck hold time t clh 90 ns cs standby pulse width t cph 90 ns cs output high impedance time t chz 150 ns sck output data time t v 80 ns output data hold time t ho 0 ns wp setup time t wps 30 ns wp hold time t wph 30 ns hold setup time t hs 30 ns hold hold time t hh 30 ns hold output low impedance time t hlz 50 ns hold output high impedance time t hhz 100 ns write cycle time t wc 10 ms sck output low impedance time t clz 0 ns ac characteristics (at fclk = 3mhz)/v dd = 1.8v to 3.6v parameter symbol conditions min typ max unit clock frequency fclk 3mhz sck logic high level pulse width t clhi 120 ns sck logic low level pulse width t cllo 120 ns input signal rise/fall time t rf 1us cs setup time t css 100 ns sck setup time t cls 100 ns data setup time t ds 30 ns data hold time t dh 50 ns cs hold time t csh 100 ns sck hold time t clh 150 ns cs standby pulse width t cph 120 ns cs output high impedance time t chz 200 ns sck output data time t v 150 ns output data hold time t ho 0 ns wp setup time t wps 30 ns wp hold time t wph 30 ns hold setup time t hs 30 ns hold hold time t hh 30 ns hold output low impedance time t hlz 120 ns hold output high impedance time t hhz 120 ns write cycle time t wc 10 ms sck output low impedance time t clz 0 ns
LE25LA322 no.na1310-5/14 table 1 command settings command 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle nth bus cycle write enable (wren) 06h write disable (wrdi) 04h status register read (rdsr) 05h status register write (wrsr) 01h data read (read) 03h a15-a8 a7-a0 write (write) 02h a15-a8 a7-a0 pd *1 pd *1 pd *1 pd *1 explanatory notes for table 1 the ?h? following each code indicates that the number given is in hexadecimal notation. addresses a15 - a12 for all commands are ?don?t care.? *1: ?pd? stands for page program data. any amoun t of data from 1 to 32 bytes is input. figure 2 serial input timing (spi mode 0) cs t css t clhi t cllo t csh t clh t cph t dh t ds data valid high impedance high impedance t cls sck si so (spi mode 3) t cllo t clhi t csh t clh t cph t dh t ds data valid high impedance high impedance t css t cls cs sck si so
LE25LA322 no.na1310-6/14 figure 3 serial output timing (spi mode 0) cs sck so si t clz t ho t chz data valid t v (spi mode 3) cs sck so si t clz t ho t chz data valid t v
LE25LA322 no.na1310-7/14 description of commands and their operations ?table 1 command settings? provides a list and overview of the commands. a detailed description of the functions and operations corresponding to each command is presented below. 1. read (read) consisting of the first through third bus cycles, the read command inputs the 16-bit addresses following (03h), and the data in the designated addresses is output synchronized to sck. the data is output from so on the falling edge of third bus cycle bit0 as a reference. ?figur e 4 read? shows the timing waveforms. when sck is input continuously after the read command has been input and the data in the designated addresses has been output, the address is automatically incremented inside the device while sck is being input, and the corresponding data is output in sequence. if the sck input is continued after the internal address arrives at the highest address, the internal address returns to the lowest addre ss (0000h), and data output is continued. by setting the logic level of cs to high, the device is deselected, and the read cycle ends. while the device is deselected, the output pin so is in a high-impedance state. figure 4 read cs sck si so mode3 high impedance 8clk mode0 0 1 2 3 4 5 6 7 8 15 16 add. (00000011) add. 23 24 25 26 27 28 29 30 31 7654 data out(n) data out(n+1) 32107 03h (a15-a8) (a7-a0) ? addresses a15 - a12 are ?don?t care.? ? in synchronization with the rising edges of 0 to 23 clock signals, the command is identified and the addresses are taken in through si. ? in synchronization with the falling edges of 23 cl ock signal or later, the data is output to so.
LE25LA322 no.na1310-8/14 2. status registers the status registers read the operating and setting statuses inside the device from outside (status register read) and set the protect information (status register write). there are 8 bits in total, and ?table 2 status registers? gives the significance of each bit. table 2 status registers bit name logic function power-on time information 0 ready bit0 rdy 1 busy (in write operation) 0 0 write disabled bit1 wen 1 write enabled 0 0 bit2 bp0 1 nonvolatile information 0 bit3 bp1 1 block protect information see status register description on bp0 and bp1 nonvolatile information bit4 0 reserved bit 0 bit5 0 reserved bit 0 bit6 0 reserved bit 0 0 status register write enabled bit7 srwp 1 status register write disabled nonvolatile information 2-1. status register read (rdsr) the contents of the status registers can be read using the status register read command. this command can be executed even during write operation. ?figure 5 status register read? shows the timing waveforms of status register read. consisting only of the first bus cycle, the status register command outputs the contents of th e status registers synchronized to the falling edge of the clock (sck) with which the eighth bit of (05h) has been input. in terms of the output sequence, srwp (bit7) is the first to be output, and each time one clock is input, all the other bits up to rdy (bit0) are output in sequence, synchronized to the falling clock edge. if the clock input is continued after rdy (bit0) has been output, the data is output by returning to the bit (srwp) that was first output, after which the output is repeated as long as the clock input is continued. the data can be read by the status register read command at any time. figure 5 status register read cs sck si so 0 mode3 8clk hight impedance status register out 765432107 05h mode0 12345 678 9101112131415 (00000101)
LE25LA322 no.na1310-9/14 2-2. status regi ster write (wrsr) the information in status registers bp 0, bp1, and srwp can be rewritten usin g the status register write command. rdy, wen, bit4, bit5, and bit6 are read-only bits and cannot be rewritten. the information in bits bp0, bp1, and srwp is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-down. ?figure 6 status register write? shows the timing waveforms of status register write, and figure 11 shows a status register write flowchart. consisting of the first and second bus cycles, the status register write command initiates the internal write operation at the rising cs edge after the data has been input following (01h). by the operation of this command, the information in bits bp0, bp1, and srwp can be rewritten. since bits rdy (bit0), wen (bit1), bit4, bit5, and bit6 of the status register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the status register. status register write ends can be detected by rdy of status register read. information in the status register can be rewritten 1,000 times (min.). to initiate status register write, the logic level of the wp pin must be set high and the status register wen must be set to ?1?. figure 6 status register write 012345678 15 mode3 t wps 8clk hight impedance data t wph self-timed write cycle t srw 01h mode0 cs wp sck si so (00000001) 2-3. contents of each status register rdy (bit0) ready/busy detection the rdy register is for detecting the write end. when it is ?1?, the device is in a busy state, and when it is ?0?, it means that the write operation is completed. wen (bit1) write enable the wen register is for detec ting whether the device can perform write operations. if it is set to ?0?, the device will not perform the write operation even if the wr ite command is input. if it is set to ?1 ?, the device can perform write operation in any area that is not block-protected. wen can be controlled using the write enable and write disable commands. by inputting the write enable command (06h), wen can be set to ?1?, and by inputting the write disa ble command (04h), it can be set to ?0?. in the following states, wen is automatically set to ?0? in order to protect against unintentional writing. ? at power-on ? upon completion of write ? upon completion of status register write ? if a write operation has not been perfor med inside the device because, for inst ance, the command input for any of the write operations has failed or a write operation has been perf ormed for a protected address, wen will retain the status established prior to the issue of the command concerned. furt hermore, its state will not be changed by a read operation.
LE25LA322 no.na1310-10/14 bp0, bp1 (bits2, 3) block protect settings block protect bp0 and bp1 are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. for the setting conditions, refer to ?table 3 protect level setting conditions.? table 3 protect level setting conditions status register bits protection block (level) bp1 bp0 protected area 0 (whole area unprotected) 0 0 none 1 (upper 1/4 area protected) 0 1 0c00h to 0fffh 2 (upper 1/2 area protected) 1 0 0800h to 0fffh 3 (whole area protected) 1 1 0000h to 0fffh srwp (bit7) status register write protect settings status register write protect srwp is the bit for protecting the status registers, and its information can be rewritten. when srwp is ?1? and the logic level of the wp pin is low, the status register write command is ignored, and status registers bp0, bp1, bp2, and srwp are protected. when the logic level of the wp pin is high, the status registers are not protected regardless of the srwp state. the srwp setting conditions are shown in ?table 4 srwp setting conditions.? table 4 srwp setting conditions wp pin srwp mode status register protected area unprotected area 1 0 0 0 1 1 software protected (spm) unprotected protected unprotected 0 1 hardware protected (hpm) protected protected unprotected bit4, bit5, and bit6 are reserved bits, and have no significance. 3. write enable (wren) before performing any of the operations listed below, the device must be placed in the write enable state. operation is the same as for setting status register wen to ?1?, and the state is enabled by inputting the write enable command. ?figure 7 write enable? shows the timing waveforms when th e write enable operation is performed. the write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). ? write (write) ? status register write (wrsr) 4. write disable (wrdi) the write disable command sets status register wen to ?0 ? to prohibit unintentional writing. ?figure 8 write disable? shows the timing waveforms. the write disable command consis ts only of the first bus cycle, and it is initiated by inputting (04h). the write disable state (wen ?0?) is exited by settin g wen to ?1? using the write enable command (06h). figure 7 write enable figure 8 write disable cs sck si so 8clk 06h high impedance mode3 mode0 01 23 456 7 (00000110) cs sck si so 8clk 04h high impedance mode3 mode0 01234 567 (00000100)
LE25LA322 no.na1310-11/14 5. write (write) the LE25LA322 enables pages with up to 32bytes to be written. any number of bytes from 1 to 32bytes can be written within the same sector page (page addresses : a15 to a5 ). ?figure 9 write? shows the write timing waveforms, and figure 12 shows a write fl owchart. after the falling cs edge, the command (02h) is input followed by the 16-bit addresses (add). the write data is then loaded until the ri sing cs edge, and the intern al addresses (a4 to a0) are incremented (add+1) every time the data is loaded in 1-byte increments. the data loading continues until the rising cs edge. if the data loaded has exceeded 32bytes, the 32bytes load ed last are written. the writ e data must be loaded in 1-byte increments, and the write operation is not performed at the rising cs edge occurring at any other timing. the write time is 10ms (max.) when 32bytes (1page) are written at one time. figure 9 write ? addresses a15 - a12 are ?don?t care .? 6. hold function using hold pin, the hold function suspends serial communication (it places it in the hold status). ?figure 10 hold? shows the timing waveforms. the device is placed in the hold status at the falli ng hold edge while the logic level of sck is low, and it exits from the hold status at the rising hold edge. when the logic level of sck is high, hold must not rise or fall. the hold function takes effect when the logic of cs is low, and the hold status is exited and serial communication is reset at the rising cs edge. in the hold st atus, the so output is in the high-impedance state, and si and sck are ?don?t care.? figure 10 hold cs hold sck so active active hold t hs t hs t hh t hlz t hh t hhz high impedance cs sck si so 8clk high impedance mode3 mode0 012345678 1516 2324 3132 3940 47 279 self-timed write cycle t wc 02h add. add. pd pd pd pd (00000010) (a15-a8) (a7-a0) (n) (n+1) (n+2) (n+31)
LE25LA322 no.na1310-12/14 7. hardware data protection in order to protect against unintentional writing at power-o n, the LE25LA322 incorporates a power-on reset function. 8. software data protection this product eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. ? when a write command is input and the rising cs edge timing is not in a bus cycle (8clk units of sck). ? when the write data is not in 1-byte increments. ? when the status register write command is input for 2bus cycles or more. 9. power-on in order to protect against unintentional writing, cs must be kept at v dd at power-on. after power-on, the supply voltage has stabilized at 1.8v or higher, wait for 10 s (t pu _read) before inputting the command to start a read operation. similarly, wait for 10ms (t pu _write) after the supply voltage has stabilized at 1.8v or higher before inputting the command to start a write operation. 10. decoupling capacitor a0.1 f ceramic capacitor must be provided to each device and connected between v dd and v ss in order to ensure that the device will operate stably.
LE25LA322 no.na1310-13/14 figure 11 status register write fl owchart figure 12 write flowchart status register write set status register write command set write enable command start 05h program start on rising edge of cs end of status re g ister write yes bit 0= ?0? ? 06h 01h no *automatically placed in write disabled state at the end of the status register write. data set status register read command write start 05h set write command a ddress 1 a ddress 2 write start on rising edge of cs end of write yes bit 0= ?0? ? data 0 06h set write enable command 02h no data 1 data n *automatically placed in write disabled state at the end of the write. set status register read command
LE25LA322 no.na1310-14/14 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. application note 1) precautions at power-on in order to protect against unintentional writing, the le25 la322 incorporates a power-on rest circuit. the following conditions must be met in order to ensure that the power-on reset circuit will operate stably. no guarantees are given for data in the event of an instantaneous power failure occurring during the write operation. v dd = 1.8 to 3.6v symbol item min typ max unit t rise power rise time 100 ms t off power off time 10 ms vbot power bottom voltage 0.2 v v dd t off vbot t rise 0v note: 1). the cs pin must be set high. this catalog provides information as of january, 2011. specifications and information herein are subject to change without notice.

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